Chiplet connection technology is heading towards commercialization

Growing interest in chiplet technology for high-performance computing architectures has driven both development at start-up companies and increased funding activity. One of these companies, Eliyan Corporation, recently closed a $40 million Series A funding round and is poised to commercialize a chiplet interconnect technology called NuLink that achieves high performance using commodity organic substrates.

Eliyan was founded by CEO Ramin Farjadrad, the inventor of the Bunch of Wires (BoW) scheme adopted by the Open Compute Project (OCP). NuLink technology is backward compatible with Universal Chiplet Interconnect Express (UCIe), a standard developed by Intel and donated to the UCIe Consortium. According to Farjadrad, the technology achieves similar bandwidth, power efficiency, and latency as die-to-die implementations using advanced packaging technologies, but without the other drawbacks of more specialized approaches.

Eliyan’s BoW approach is specifically designed to meet the need for high-efficiency Die-to-Die (D2D) PHYs to connect different functions in one package. NuLink technology, which is a superset of BoW and UCIe, uses patented implementation techniques to enable wide performance differentiation for D2D connectivity across each package substrate, reducing complexity and lowering overall development time and cost.

Farjadrad said in an interview with Design News the technology eliminates the need for advanced packaging solutions, most commonly silicon interposers, which limit the overall size of the system-in-package, which ultimately limits performance. The use of interposers also limits wafer test coverage, ultimately impacting yield, increasing total cost of ownership, and increasing overall manufacturing cycle time.

Instead of using interposers, NuLink uses a patented Gearbox scheme that acts as an adapter to connect any off-the-shelf micro-bump chiplets via standard-bump organic substrate. This technique eliminates the need for a large, complex silicon interposer. This optimized technology for 2.5/3D package implementations allows for a practical mixing and matching of chiplets with different die-to-die interfaces in different processes (DRAM, SOI, etc.).

The technology has been developed by Farjadrad and his team since 2017. In 2018, Farjadrad proposed BoW as a superior chiplet interconnect architecture for OCP. The improved performance and features that BoW offers over existing processes received strong support and was eventually adopted as OCP’s chiplet interconnect scheme.

A previous incarnation of NuLink technology was mass-produced in a 14nm process, confirming its commercial viability and performance benefits. The latest version, taped to 5nm, delivers at least 2000 Gbps/mm edge bandwidth on a standard organic package.

Eliyan expects its first silicon in the first quarter of 2023.

The ramp-up of Eliyan’s technology points to a bright future for chiplet technology, which is seen as an important means of developing custom chips to help product designers scale the performance, power efficiency and size needed for high-performance computing applications required are.

Earlier this year, a group of leading technology companies recently formed an industry consortium called the UCIe Consortium to establish a die-to-die interconnect standard and promote an open chiplet ecosystem.

Spencer Chin is Senior Editor for Design News and covers the electronic beat. He has extensive experience in developing components, semiconductors, subsystems, power supply and other facets of electronics from both a business/supply chain and technology perspective. He can be reached at [email protected]

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